The present invention relates to switching power supplies, and in particular, to the switch control circuitry in a switching power supply.
Low-voltage, high-speed computer processors present an array of complex power supply design challenges including multiple voltages, high currents, precise regulation, low noise, fast response, tight space, and cost constraints. For example, the core of a 300 MHz Intel Pentium(copyright) II processor draws up to 14.2A at a typical voltage of 2.8v, and can generate current transients of up to 13A at 30A/xcexcsec. Future processors are likely to produce even higher rates of current consumption and even more severe load transients. Maintaining desirable regulation under such high current loads and such wide load swings pushes beyond the practical limits of conventional linear regulators. Their efficiency is too low, producing excessive heat, and requiring costly power dissipation hardware. Consequently, the trend for such applications has been to use DCxe2x80x94DC switching regulators, or converters, e.g., synchronous and nonsynchronous buck converters.
A buck converter works by varying the duty cycle of the power MOSFET switch it drives. For example, in a synchronous topology as shown in FIG. 1(a), switch Q1 turns on at the start of each switching cycle. A voltage equal to the supply voltage less the output voltage appears across the inductor, L. The resulting inductor current climbs and flows through the load as long as the switch Q1 is closed. The current ramp is approximated by:
xcex94ION=[tONxc3x97xcex94V]/L
where xcex94ION is the current through the inductor, tON is the switch on time, xcex94V is the voltage across the inductor, and L is the inductance. When Q1 is off, Q2, the synchronous rectification transistor, turns on and energy stored in the inductor L generates current through Q2 and the load. The output voltage appears across the inductor, causing a current ramp approximated by:
xcex94IOFF=[tOFFxc3x97VOUT]/L
During each switching cycle, the inductor""s steady-state current ramps between maximum and minimum values, yielding an average current of:
IDC=(IMAX+IMIN)/2
Because xcex94ION=xcex94IOFF,
TONxc3x97(VINxe2x88x92VOUT)=TOFFxc3x97VOUT
Thus, the volt-second product is the same during the power switch""s on and off times. However, because the average inductor current equals the load current, inductor ripple current can flow through the load to ground during the power switch""s off time, degrading efficiency. This is not the case for a nonsynchronous buck converter, as shown in FIG. 1(b), which replaces Q2 with a diode.
Input voltage and output voltage are related to duty cycle, which is the ratio of the power switch""s on time over the total switching period:
Duty Cycle=VOUT/VIN
Duty cycle is a function of the input and output voltages, and is independent of the load. In practice, under heavy loads, voltage across the inductor is reduced by resistive losses in the two MOSFET switches, circuit board traces, and the inductor itself. In addition, input voltage tends to drop with increased load. These loading losses can cause duty cycle to vary by 25% or more.
Compared to linear regulators, buck converters, because of their switching inductance, have an inherently slower output current slew rate. However, a converter""s finite transient response time can be enhanced by bulk output capacitance, improving overall response to instantaneous load changes. The minimum theoretical transient response is given by:
tRESPONSE=(xcex94Ixc3x97L)/xcex94V
where xcex94I is the change load current, xcex94V is the voltage across the inductor, and L is the inductance. For example, if VIN=5v, VOUT=2.8v, and L=2 xcexcH, and load changes from 0.5A to 13A, the minimum transient response time is 11.4 xcexcs.
However, the duty cycle control loops of conventional buck converters tend to operate at relatively low frequencies, and, therefore, theoretical minimum transient response times are not approached. Typically, the linear loops adjust to load changes over hundreds of microseconds and many switching cycles. To meet the fast response time of modern computer processors, such buck converter circuits require many costly, low equivalent series resistance (ESR) capacitors. A review of the most common control schemes illustrates the problem.
Of the three common control methods for buck convertersxe2x80x94voltage mode, current mode, and ripple regulationxe2x80x94voltage mode control, shown in FIG. 2, is widely favored for its simple feedback loop. An error amplifier compares the regulator output voltage to a reference voltage, and generates a control voltage which drives one input of a comparator. The other input to the comparator is connected to a sawtooth wave generator oscillator. The comparator and its inputs serve as a pulse-width modulator (PWM) circuit that controls the MOSFET switch on-time and, therefore, its duty cycle and output voltage.
At the start of each switching cycle, with the MOSFET switched on, the sawtooth voltage ramps upward from its minimum level. When the sawtooth reaches the error amplifier output voltage level, the comparator turns off the MOSFET. This method of control requires that the error amplifier adjust its output voltage in response to line and load changes. Changes in the control voltage pass through the error amplifier and cause corresponding changes in the output voltage. For DC accuracy and stability, voltage mode control requires the control loop to have a relatively high gain and low frequency response, thereby limiting transient response.
Current mode control, shown in FIG. 3, employs dual feedback loops and offers improved line regulation. As with voltage control, this technique uses an error amplifier to generate a PWM control voltage. However, the current through the inductor becomes the source of the PWM sawtooth waveform. Because changes in input voltage immediately affect the slope of the inductor ramp current, duty cycle is inherently adjusted without requiring a change in the error amplifier output. Changes in the load, however, do not affect inductor current or the PWM ramp. Consequently, as with voltage mode control, load regulation requires changes in the error amplifier output voltage. Also, current mode control needs an accurate (and often bulky and costly) current sense resistor to produce a stable PWM ramp voltage, thereby reducing efficiency.
Ripple regulation, shown in FIG. 4, uses output voltage ripple as the PWM sawtooth which is fed to the PWM comparator. The control signal at the other comparator input is a fixed voltage. As a result, ripple regulation requires no error amplifier and achieves a fast response without the need for loop compensation. The MOSFET duty cycle adjusts quickly, pulse by pulse. Changes in line current immediately affect the inductor current and correct the output voltage. Changes in load correct the output directly. The design is simple and its component count low. The main drawback of ripple regulation, however, is that it controls the peak output ripple voltage. Thus, DC accuracy is determined by the mean output ripple voltage, and, as a result, regulation suffers. Related regulation problems include increased output voltage caused by PWM comparator and switch delays, as well as output voltage decreases caused by aging output capacitors.
A fourth method of buck converter controlxe2x80x94V2(trademark) controlxe2x80x94combines the simple, fast response, and low component count of ripple regulation with the DC accuracy of voltage mode control. The V2(trademark) method, shown in FIG. 5, adds an error amplifier to the ripple regulator topology, resulting in dual feedback loops as in current mode control. The output voltage generates both the ramp signal and the error signal. The V2(trademark) method of control uses a ramp signal generated by the ESR of the output capacitors. This ramp is proportional to the AC current in the inductor and is offset by the DC output voltage. V2(trademark) inherently compensates for variation in both line and load conditions since the ramp signal is generated from the output voltage. This differs from traditional methods such as voltage mode control, where an artificial ramp signal must be generated, and current mode control, where a ramp is generated from inductor current.
The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the output switch from 0% to about 90% duty cycle. Changes in line voltage will change the current ramp in the inductor, affecting the ramp signal and causing the V2(trademark) control loop to adjust the duty cycle. Since a change in inductor current changes the ramp signal, the V2(trademark) method has the characteristics and advantages of current mode control for line transient response. Changes in load current will affect the output voltage and thus will also change the ramp signal. A load step will immediately change the state of the comparator output that controls the output switch. In this case, the comparator response time and the transition speed of the switch limit load transient response time. The reaction time of the V2(trademark) loop to a load transient is not dependent on the crossover frequency of the error signal loop whereas traditional voltage mode and current mode methods are dependent on the compensation of the error signal loop.
The V2(trademark) error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. The xe2x80x9cslowxe2x80x9d error signal loop provides DC accuracy. Low frequency roll-off of the error amplifier bandwidth will significantly improve noise immunity. This also improves remote sensing of the output voltage, since switching noise picked up in long feedback traces can be effectively filtered.
V2(trademark) line regulation and load regulation are improved because there are two separate control loops. A voltage mode controller relies on a change in the error signal to indicate a change in the line and/or load conditions. The error signal change causes the error loop to respond with a correction that is dependent on the gain of the error amplifier. A current-mode controller has a constant error signal during line transients, since the slope of the ramp signal will change in this case. However, regulation of load transients still requires a change in the error signal. V2(trademark) control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both.
One embodiment of the present invention includes a novel gate drive circuit for a switching power supply. The power supply has an output inductor connected at one end to a power switch circuit having a duty cycle, the other end of the output inductor having a regulated output voltage. The gate drive circuit includes an error amplifier that produces an error signal representative of the difference between a reference voltage and a voltage feedback signal representative of the regulated output voltage. A pulse width modulator comparator that compares the error signal to a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of output inductor current, the composite signal having an ac component and a dc component, the comparator output resulting in a gate drive signal that controls the duty cycle of the power switch circuit to maintain the regulated output voltage.
In a further such embodiment, an adaptive voltage positioning circuit adjusts the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when the output inductor current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when the output inductor current is more than the nominal current. The adaptive voltage positioning circuit may use a resistance network, and/or, control output impedance of the power switch circuit based on scaling of the current sensing signal.
An embodiment may further include an overcurrent protection circuit that causes the comparator to turn off the power switch circuit when the current sensing signal exceeds a maximum current reference voltage. The comparator output may determine when the gate drive signal turns off the power switch circuit, in which case, a constant frequency oscillator signal may determine when the gate drive signal turns on the power switch circuit.
Another embodiment of the present invention includes a novel method of generating a gate drive signal for a switching power supply, the power supply having an output inductor connected at one end to a power switch circuit having a duty cycle, the other end of the output inductor having a regulated output voltage, The method includes producing an error signal representative of the difference between a reference voltage and a voltage feedback signal representative of the regulated output voltage; and comparing the error signal to a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of output inductor current, the composite signal having an ac component and a dc component, to produce a signal for generating a gate drive signal that controls the duty cycle of the power switch circuit to maintain the regulated output voltage.
A further such embodiment, may also include adjusting the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when the output inductor current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when the output inductor current is more than the nominal current. Adjusting the voltage feedback signal may include using a resistance network, and/or, use scaling of the current sensing signal to control output impedance of the power switch circuit.
An embodiment may further include providing overcurrent protection by causing the gate drive signal to turn off the power switch circuit when the current sensing signal exceeds a maximum current reference voltage. The signal produced by comparing may determine when the gate drive signal turns off the power switch circuit, in which case, the gate drive signal may turn on the power switch circuit according to a constant frequency oscillator signal.
Another embodiment of the present invention includes a multi-phase gate drive circuit for a switching power supply, the power supply having a plurality of parallel output inductors, each inductor being connected at one end to an associated power switch circuit having a duty cycle, the other end of each inductor being connected to an electrically common point having a regulated output voltage. The gate drive circuit includes an error amplifier circuit that produces an error signal representative of the difference between a reference voltage and a voltage feedback signal representative of the regulated output voltage; and a pulse width modulator comparator for each power switch circuit, each comparator comparing the error signal to a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of current of the associated output inductor, the composite signal having an ac component and a dc component, each comparator producing a signal for generating a gate drive signal that controls the duty cycle of the associated power switch circuit to maintain the regulated output voltage.
Such an embodiment may further include an adaptive voltage positioning circuit that adjusts the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when output current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when output current is more than the nominal current. The adaptive positioning circuit may use a resistance network, and/or, control output impedance of the associated power switch module based on scaling of the associated current sensing signal.
In a further embodiment, each of the plurality of parallel output inductors may be limited to the same peak current based on output impedance of the associated power switch circuit. An overcurrent protection circuit may cause a comparator to turn off its associated power switch circuit when the associated current sensing signal exceeds a maximum current reference voltage. A current limiting circuit may cause each comparator to turn off its associated power switch circuit when a signal representing a sum of the average current of each power switch circuit exceeds an overcurrent reference signal. The signal produced by each comparator may determine when the associated gate drive signal turns off its associated power switch circuit, in which case, a constant frequency oscillator signal may determine when each gate drive signal turns on its associated power switch circuit.
An embodiment of the present invention includes a switching power supply for producing a regulated output voltage. The power supply includes an output inductor connected at one end to a power switch circuit having a duty cycle, the other end of the output inductor having a regulated output voltage. A voltage feedback circuit voltage feedback circuit coupled to the other end of the output inductor produces a voltage feedback signal representative of the regulated output voltage. A current feedback circuit coupled to both ends of the output inductor produces a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of output inductor current, the composite signal having an ac component and a dc component. An error amplifier produces an error signal representative of the difference between a reference voltage and the voltage feedback signal. A pulse width modulator comparator compares the error signal to the composite signal, the comparator output resulting in a gate drive signal that controls the duty cycle of the power switch circuit to maintain the regulated output voltage.
In a further embodiment, the current feedback circuit may include an RC filter, or a voltage divider. The power switch circuit may further include two semiconductor switches connected in series to form a common terminal connected to the output inductor. An adaptive voltage positioning circuit may adjusts the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when the output inductor current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when the output inductor current is more than the nominal current. The adaptive voltage positioning circuit may use a resistance network, and/or, control output impedance of the power switch circuit based on scaling of the current sensing signal.
A further embodiment may include an overcurrent protection circuit that causes the comparator to turn off the power switch circuit when the current sensing signal exceeds a maximum current reference voltage. The comparator output may determine when the gate drive signal turns off the power switch circuit, in which case, a constant frequency oscillator signal may determine when the gate drive signal turns on the power switch circuit.
An embodiment of the present invention includes a multi-phase switching power supply for producing a regulated output voltage. The power supply includes a plurality of output inductors connected in parallel, each inductor being connected at one end to an associated power switch circuit having a duty cycle, the other end of each inductor being connected to an electrically common point having a regulated output voltage. A voltage feedback circuit coupled to the electrically common point that produces a voltage feedback signal representative of the regulated output voltage. A current feedback circuit for each output inductor, coupled to both ends of each respective inductor, that produces a composite signal representing a summing of the voltage feedback signal with a current sensing signal representative of current of the associated output inductor, the composite signal having an ac component and a dc component. A pulse width modulator comparator for each power switch circuit compares the error signal to the associated composite signal to produce a signal for generating a gate drive signal that controls the duty cycle of the associated power switch circuit to maintain the regulated output voltage.
In a further embodiment, the current feedback circuit includes, for each output inductor, an RC filter, or a voltage divider. Each power switch circuit may include two semiconductor switches connected in series to form a common terminal connected to the associated output inductor. In addition, an adaptive voltage positioning circuit may adjust the voltage feedback signal to increase the regulated output voltage above a nominal output voltage when output current is less than a nominal current, and to decrease the regulated output voltage below the nominal output voltage when output current is more than the nominal current. The adaptive voltage positioning circuit may uses a resistance network, and/or, control output impedance of a power switch module based on scaling of the associated current sensing signal.
An embodiment may also include an overcurrent protection circuit that causes a comparator to turn off its associated power switch circuit when the associated current sensing signal exceeds a maximum current reference voltage. A current limiting circuit may cause each comparator to turn off its associated power switch circuit when a signal representing a sum of the average current of each power switch circuit exceeds an overcurrent reference signal. The comparator output may determine when the gate drive signal turns off its associated power switch circuit, in which case, a constant frequency oscillator signal may determine when the gate drive signal turns on its associated power switch circuit.